Examples of a solid-state imaging apparatus that images an image may include a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor. In recent years, the CMOS image sensor has attracted attention for requests such as downsizing.
The CMOS image sensor includes an analog to digital (AD) conversion section (hereinafter, referred to as an AD conversion section). The AD conversion section performs AD conversion on an analog electric signal supplied from a pixel that performs photoelectric conversion. A so-called column-parallel AD conversion section is employed as the AD conversion section of the CMOS image sensor for requests such as process acceleration. (for example, PTL 1).
The column-parallel AD conversion section is able to perform AD conversion, for each column, on electric signals supplied from two or more (for example, all) pixels of a pixel group arranged in each row. For example, in the column-parallel AD conversion section, AD converters (ADCs: Analog-to-digital converters) of the number equivalent to the number of columns of the pixels are arranged side by side along the row direction. Each of the ADCs is configured to perform AD conversion of the electric signal that is supplied from a pixel of corresponding column.
Examples of the ADC may include a so-called reference signal comparative ADC. The reference signal comparative ADC includes a comparator and a counter, and compares a predetermined reference signal with an electric signal supplied from a pixel to perform the AD conversion of the electric signal. In PTL 1 mentioned above, a single slope ADC is used as the reference signal comparative ADC.
In the single slope ADC, the comparator compares a reference signal whose level is varied with a fixed gradient, such as a ramp signal, with the electric signal supplied from the pixel. The counter counts a time necessary for level change of the reference signal until the reference signal and the electric signal are coincident with each other in level. As a result, the signal is converted into a digital signal.
Sampling capacitances are coupled in series with respective paired differential input terminals of the comparator. To obtain favorable characteristics of the ADC, small fluctuation of a capacitance value (small bias dependency of the capacitance value) with respect to the input signal is desired in the sampling capacitances.
In contrast, a comb-shaped wiring capacitor (for example, PTL 2) has been proposed in which paired comb-shaped wiring lines are so oppositely disposed as to engage with each other and a parasitic capacitance caused between the opposite wiring lines is used. The comb-shaped wiring capacitor is small in bias dependency of the capacitance value and is mountable on a semiconductor substrate at a low cost.